An ongoing trend in integrated circuits (ICs) is the attempt to reduce the footprint of the IC. This is addressed, for example, by introducing new processes that allow the gate length to be reduced and thereby allow more transistors to be formed on an IC.
Another recent solution is to provide more than one die in a packaged chip, wherein the dies are stacked on top of each other and separated by an insulating material. This technology in which multiple active dies are stacked inside a single package is commonly referred to as 3D packaging. An example of such a 3D stacked die is shown in FIG. 1, which shows a bottom die 100 extending from its silicon substrate 104, which is, in turn, connected to a die paddle (not shown), which is typically made of copper.
A second die 106 is secured to the bottom die 100 by means of a Teflon based epoxy 108. A third die 110 is secured to the second die 106 by means of a Teflon based epoxy 112. A fourth, or top, die 114 is secured to the third die 110 by means of a Teflon based epoxy 116. It should be noted that the dies 106, 110, 114 in FIG. 1 have substrates too, but their substrates are thinned down to 50 um in this case before assembling. Usually, the substrate thickness of a wafer is 750 um, but is trimmed down to 400 um before it is cut to single chips for assembling as single die ICs. In the case of stacked die, however, the substrates of the dies 106, 110, 114 are thinned out even further.
Each of the dies, 100, 106, 110, and 114 has electrical contacts that are connected electrically by means of bond wires 120 to the silicon substrate 104. The entire structure, comprising the paddle 104, dies, 100, 106, 110, 114, and bond wires 120, are encased in a packaging material, typically referred to as a package (not shown in FIG. 1) and commonly made of a plastics materials. The electrical contacts for each die are typically provided along the die's periphery, and the bond wires are connected to the contacts by means of gold ball bonds (not shown). In order to avoid the top three dies 106, 110, 114 from interfering with the gold ball bonds of the respective dies immediately below them, the upper die can be made ever smaller so that the top die is the smallest, the third die the second smallest, etc. However, in the embodiment shown in FIG. 1, the dies are all the same size, and the epoxy layers 108, 112, 116 between the dies is chosen to be sufficiently thick so as to accommodate the gold ball bonds.
A problem facing the industry is in the testing of such stacked die devices after they have been stacked and packaged. It is common for faulty ICs to be returned by customers to the manufacturer for analysis to determine the root cause of the fault. In the case of non-stacked die this involves the decapping of the IC, i.e. either the top or the back of the package is removed by mechanical grinding or chemical etching. Two common techniques used are wet etch and dry etch. Wet etch includes parallel lapping and acid etching. This removes packaging materials such as plastic, copper, or ceramic. Silicon and metal aluminum will be left and not damaged. Dry etching includes RIE (reactive ion etching) and ChipUnzip (a mechanical grinding method which allows holes of any size and depth to be cut into the IC from its backside). RIE does not remove the packaging materials but serves to remove silicon dioxide. Thus, it is useful for front side electron beam probing. In situations where the bottom metal layers are blocked by the top metal layers, employing RIE to remove silicon dioxide allows operator to view the bottom metal layers from the top of the die.
With the IC exposed, areas of interest in the IC become accessible for testing. However, in the case of a stacked device, there is more than one die. Thus, at least some of the electrical contacts of the lower dies are typically covered by the dies above them and cannot be accessed. Furthermore, it is not possible to isolate the characteristics of individual devices since the functioning of devices on one die is impacted by the devices on the other dies, since the dies are interconnected to allow all of the dies to work as one large IC. This interconnection may take place externally (on the printed circuit board on which the stacked device is mounted) or internally by having vias through the epoxy between the die to thereby allow electrical connection between contacts on one die and contacts of another die. The present invention seeks to provide a way of testing such ICs with 3D packaging.